The trench power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a power semiconductor device of a new generation, which has a fast switching speed, high input resistance and negative temperature coefficient. Compared with the VDMOS (vertical conductiondouble scattering metal oxide semiconductor), the trench power MOSFET can enable chips to be made in smaller size with low RDS(on) ensured; and it is widely used in high-frequency, medium and low power fields, such as electric vehicles, mobile phones, computer power supplies, and other products.
Because of miniaturization trends of modern electronic products, components are required to have smaller physical volumes, that is, package dimensions of devices are getting smaller and smaller. In order to ensure low RDS(on), the new trench MOSFET has used smaller unit cell pitches, and recently, the smallest unit cell pitch has been able to reach about 1.1 um. However, it also brings new requirements for the manufacturing process of a device: as unit cell pitches are reduced, the controllable range of the diffusion process used during the production of source blocks will become smaller and smaller, and it is likely to cause an imperfect contact between source contact holes and the substrate of a device, which affects the test performance of the device as well as the production yield.
At present, aiming at production methods of contact holes, the self-aligned effect of side walls of the gate electrode has been utilized in large scale integrated circuit processing production to produce trench contact holes to replace the conventional plane type contact holes (refer to FIG. 1). As the trench power MOSFET is of a longitudinal structure, the production process for trench contact holes in the large scale integrated circuit processing production is not suitable for the production methods of contact holes of the trench power MOSFET; meanwhile, there are similar production processes for trench contact holes in the prior art related to trench power MOSFET process, but the production process for the trench power MOSFET with the trench contact holes comprises six photolithographic procedures as blow:
Buried layer;
Active layer;
Source implantation;
Trench;
Contact holes; and
Metal.
Wherein the contact holes are relatively large-sized, the production process is generally suitable for those trench MOSFET devices with contact holes whose sizes are more than 0.6 um. As for the contact holes whose size are 0.3 um or less than 0.3 um, the contact holes will be filled imperfect due to the use of aluminum (Al) as a metal filling medium in the prior art, which causes the appearance of voids 100 as shown in FIG. 1 and non-uniform Al step coverage, etc. As a result, the trench power MOSFET device may have reliability problems in actual use, which directly affects the application function of the device.
The prior MOS transistor source block process has the following characteristics (suitable for large unit cell pitches: 0.6 um and above), as shown in FIG. 2:
The source electrode of the MOS transistor contacts both N+ source block 100,103 and P well region 101 through the source metal 102, and the P well region is connected with the source metal 102 through the P+ doping 104 for better ohm contact; as can be seen from FIG. 2, in order that the source metal 102 can contact with both the N+ source regions 100 and 103 and the P well region 101 well, the region inside p well that encircled by N+ source block ring must be ensured to have a dimension sufficient enough in the middle to prevent the N+ source regions 100 and 103 from colliding with each other and guarantee both the P well and the N+ source block contact the source metal 102 well during the subsequent thermal process. In addition, ‘bowl-mouth-shaped’ contact holes and ‘hot aluminum’ metal deposition process are usually used to ensure good metal coverage because that metal AlSiCu is directly filled. The above two factors (namely, the ‘bowl-mouth-shaped’ contact holes and the ‘hot aluminum’ metal deposition process) cause that the unit cell pitch of a single MOS transistor cannot be designed too small, usually said pitch is no less than 2 um.
Using metal material AlSiCu as an electrode has the following defects: due to the high solubility of silicon (Si) in aluminum (Al), a Al spiking can be readily formed in Si which causes a breakdown of PN junction. Although the breakdown can be prevented by adding 1% Si into Al, still, Si will readily form Si accumulation in Al which results in larger contact resistance and other adverse effects.
Using source block photolithography to control the spacing between adjacent source blocks has the following defects: in the case of the smaller unit cell, the horizontal diffusion of N+ impurities will be more difficult to control during the thermal process of the production of source blocks, so the ion implantation into the source region is typically replaced by implanting N+ ions into the entire ‘source block island’ surrounded by ‘trenches’. However, the substrate P well will be completely isolated by the source region. If the process of contact hole as shown in FIG. 2 is still used, the P well will not be able to contact the source block, which causes undesirable ground connection, and thus deteriorates electric characteristics of the transistor.